1. Field of the Invention
The present invention relates to memory card circuits and particularly to a circuit provided in a portable memory card such as an IC card.
2. Description of the Background Art
Portable cards having a memory function (hereinafter called memory cards) such as IC cards are known in the prior art. Such a memory card has a semiconductor integrated circuit device having a memory function mounted on a card medium formed of synthetic resin or the like. A memory card is usually carried by a user and it is inserted in terminal units of various systems when it is used. Thus, the terminal unit and the semiconductor integrated circuit device of the memory card are electrically connected so that various data processing can be performed between the terminal unit and the memory card. For example, a semiconductor memory contained in a semiconductor integrated circuit device of a memory card is accessed by a terminal unit, whereby the content of the memory is read or rewritten.
FIG. 1 is a circuit diagram showing a construction of a conventional memory card circuit mounted in a memory card. Referring to FIG. 1, a static RAM group 1 has a plurality of static RAM's (hereinafter referred to as SRAM's) 2a to 2n. An address decoder 3 generates an SRAM selection signal based on address data supplied from a terminal unit, not shown, through an address bus 8 and a chip enable signal CE supplied from the terminal unit through a signal line 9. This SRAM selection signal serves to select any one of the SRAM's 2a to 2n and it is applied to CE terminals (chip enable terminals) of the respective SRAM's 2a to 2n through signal lines 13a to 13n. A write enable signal WE is applied to WE terminals (write enable terminals) of the respective SRAM's 2a to 2n through a signal line 10 from the terminal unit and an output enable signal OE is applied to OE terminals (output enable terminals) thereof through a signal line 11 from the external unit. The SRAM's 2a to 2n are connected to an I/O data bus 12. A power supply input line 14 receiving input of power from an external power supply on the side of the terminal unit is connected to an internal power supply line 15 through a diode 16. When the power supply input line 14 is in a cutoff state (a state where it does not receive input of power from the terminal unit) as in the case where the user is carrying the card, a battery 6 operates to supply electric current to the internal power supply line 15 through a resistor 5 and a protection diode 4. Thus, the battery 6 is used as an internal power supply for backup of the SRAM's 2a to 2n. A capacitor 7 is provided between the internal power supply line 15 and the ground. A pull-up resistor 17 is provided between the internal power supply line 15 and the signal lines 9, 10. The signals CE, WE, OE are "L" active signals (i.e., signals rendered active at low ("L") level).
The conventional memory card circuit shown in FIG. 1 has a minimum necessary construction for a circuit of a memory card and it is generally well known. The respective SRAM's 2a to 2n of the SRAM group 1 are directly connected to the terminal unit (not shown) through the address bus 8, the signal lines 10, 11 and the 15 I/O data bus 12 so as to communicate data or signals with the terminal unit. Thus, each of the SRAM's 2a to 2n is constructed to be directly accessed from the terminal unit. Accordingly, when any one of the SRAM's is selected by the SRAM selection signal from the address decoder 3, the SRAM group 1 performs in principle just the same operation as individual operation of a general single SRAM.
In the following, operation of the conventional memory card circuit shown in FIG. 1 will be described.
First of all, description will be made of a case where no power input is applied from a terminal unit to the power supply input line 14 as in the case of the card being carried by a user. In this case, voltage of the battery 6 is supplied to the respective SRAM's 2a to 2n and the address decoder 3 through the resistor 5 and the protection diode 4. At this time, the address decoder 3 is in a non-operating state since an E terminal (enable terminal) thereof is pulled up to high ("H") level through the resistor 17. Accordingly, the SRAM selection signals provided from the address decoder 3 to the signal lines 13a to 13n are all at "H" level. Thus, the SRAM's 2a to 2n are all in a non-selective state. The I/O data bus 12 connected to the respective SRAM's 2a to 2n is in a floating state. Thus, the data stored in the SRAM's 2a to 2n can be maintained without being erased.
Next, description will be made of a case where power supply voltage is supplied from the power supply input line 14 from a terminal unit (not shown) into which a memory card is inserted. The power supply voltage supplied to the power supply input line 14 is supplied to the internal power supply line 15 through the diode 16. In general, the voltage of the internal power supply line 15 in this case is set larger than the voltage of the battery 6 and accordingly the connection between the internal power supply line 15 and the battery 6 is cut off by means of the protection diode 4. Consequently, electric current does not flow in the battery 6 and there is no consumption of power of the battery 6.
Since read and write operations of the SRAM's 2a to 2n are the same as the operations of a single general SRAM as described previously, only a brief description thereof will be given in the following.
First of all, address data is inputted to the address bus 8 from a terminal unit not shown and it is supplied to the address decoder 3 and the SRAM's 2a to 2n. The address decoder 3 decodes the address data and sets only the SRAM selection signal applied to a corresponding SRAM 2k (any one of 2a to 2n) to an active state, namely "L" level. The address decoder 3 sets the above mentioned SRAM selection signal to the active state only when the chip enable signal CE supplied through the signal line 9 is at "L" level. Now, let us assume that the corresponding SRAM 2k is selected by the address decoder 3. In other words, it is assumed that the CE terminal of the SRAM 2k is at "L" level. It is possible to write data into a storage area of the SRAM 2k from the terminal unit (through the I/O data bus 12) by setting a write enable signal WE to "L" level in a period of "L" level of the chip enable signal CE. In this case, an output enable signal OE is set to "H" level. It is possible to read the data from the storage area of the SRAM 2k by setting the output enable signal OE to "L" level in a period of "L" level of the chip enable signal CE. In this case, the write enable signal WE is set to "L" level. If the chip enable signal CE inputted to the signal line 9 is raised to "H" level, the I/O data bus 12 of the SRAM's 2a to 2n is brought into the floating state, making it impossible to read or write any data. Those operations are the same as the operation of a single general SRAM and therefore well known.
It is pointed that the conventional memory card circuit shown in FIG. 1 has the below described problems (1) to (5).
(1) The respective SRAM's 2a to 2n are connected directly to a terminal unit through the address bus 8, the signal lines 9 to 11 and the I/O data bus 12 so as to communicate data and signals with the terminal unit. Consequently, when a memory card is inserted into or taken out from a terminal unit which is in operation (namely, in a conducted state), irregularities occur in the levels of the input/output signals of the respective SRAM's 2a to 2n due to a defective contact, a transient phenomenon or the like in a portion of connection between the memory card and the terminal unit. More specifically, when the card is inserted into or detached from the terminal unit, the respective input/output signals do not change with the same level and differences occur in a short time. As a result, the data stored in the SRAM's 2a to 2n would be damaged.
(2) In case where input of power from the terminal unit to the power supply input line 14 is interrupted while the terminal unit and the memory card are connected, electric current from the battery 6 flows into the terminal unit through the resistor 5, the protection diode 4 and the pull-up resistor 17 if the potential of the signal line 9 or the signal line 10 is "L" level. As a result, the battery 6 has discharged and consumed instantaneously.
(3) Since the respective SRAM's 2a to 2n are constructed to be directly connected with a terminal unit, electrostatic strength of the memory card depends on electrostatic strength of each SRAM.
(4) Since input/output impedance of the memory card which is carried with the user depends on impedances of the respective single SRAM's 2a to 2n and the address decoder 3, the input/output impedance of the memory card is generally a very high impedance. Consequently, the electrostatic strength and electromagnetic filed strength of the memory card are low values.
(5) If the number of SRAM's included in the SRAM group 1 is increased, the input/output capacitance of each signal in the signal lines 9 to 11 and the I/O data bus 12 increases. As a result, the rise and fall periods of each signal become very long and the rated values of the respective SRAM's 2a to 2n are not satisfied. Consequently, the electric performance of the memory card is considerably deteriorated.